This invention relates generally to ferroelectric films and ferroelectric capacitors. More particularly, the present invention relates to a measurement method for characterizing the retention performance and imprint degradation of the ferroelectric film, as well as other performance aspects.
Ferroelectric thin films are a class of polar dielectric materials whose spontaneous polarization can be reversed with the application of an externally applied electric field. Because the polarization is spontaneous, the dipoles remain in the poled state upon removal of the electric field. The ability of a ferroelectric thin film to retain a poled state indefinitely forms the basis for its implementation as a nonvolatile memory cell element. The reversal of spontaneous polarization in a ferroelectric thin film is termed "switching." The phenomenon of ferroelectricity derives its name from ferromagnetics in that both possess domains, exhibit hysteresis under applied fields, and show Curie-Wiess behavior near the phase transition.
To quantify switching, measurements are carried out with the Sawyer-Tower test configuration 10 shown in FIG. 1. The Sawyer-Tower test configuration 10 includes a pulse generator 12, which can generate both positive-going and negative-going voltage pulses; a ferroelectric capacitor 14 desired to be characterized, designated C.sub.FE ; a standard "linear" load capacitor 16 designated C.sub.L ; and a digital oscilloscope 18. Inputs 20 and 22 of digital oscilloscope 18 are coupled across ferroelectric capacitor 14. It is desirable that the ratio of the values of the C.sub.L load capacitor 16 to the C.sub.FE ferroelectric capacitor 14 be greater than ten so that most of the input pulse voltage is dropped across load capacitor 16.
A pulse sequence 24 shown in FIG. 2A is applied to one of the terminals of ferroelectric capacitor 14. Pulse sequence 24 includes an initial pulse 26, followed by four pulses 28, 30, 32, and 34, which are used to characterize the electrical performance of ferroelectric capacitor 14. The initial pulse 26 is used to set the polarization state of ferroelectric capacitor 14. The charge associated with the leading edge of pulse 26 is termed "N" and the charge associated with the trailing edge of pulse 26 is termed "N.sub.A ", read "N after." If ferroelectric capacitor 14 is in a virgin state, however, the charge associated with the leading edge of pulse 26 is indeterminate. Thereafter, pulses 28-34 are used to traverse the full "hysteresis loop" 36 associated with ferroelectric capacitor 14. Note that while the hysteresis loop 36 can be traversed with two pulses, four pulses are required to acquire all four "P", "U", "N", and "D" charge components. These four charge components are explained in further detail below. The hysteresis loop 36 is used to characterize the electrical performance of ferroelectric capacitor, and is shown in FIG. 3.
Returning to FIG. 2A, a first positive-going pulse 28 is applied to ferroelectric capacitor 14. The charge associated with the leading edge of pulse 28 is termed "P" and the charge associated with the trailing edge of pulse 28 is termed "P.sub.A ", read "P after." A second positive-going pulse 30 is then applied to ferroelectric capacitor 14. The charge associated with the leading edge of pulse 30 is termed "U" and the charge associated with the trailing edge of pulse 30 is termed "U.sub.A ", read "U after." A first negative-going pulse 32 is then applied to ferroelectric capacitor 14. The charge associated with the leading edge of pulse 32 is termed "N" and the charge associated with the trailing edge of pulse 32 is termed "N.sub.A ", read "N after." A second negative-going pulse 34 is then applied to ferroelectric capacitor 14. The charge associated with the leading edge of pulse 34 is termed "D" and the charge associated with the trailing edge of pulse 34 is termed "D.sub.A ", read "D after." The sequence of four pulse 28, 30, 32, and 34 are used to completely traverse the hysteresis loop associated with ferroelectric capacitor 14, and are often referred to simply as the P (for positive), U (for up), N (for negative), and D (for down) pulses, respectively, or simply as the "PUND" waveform. Correspondingly, a P pulse is a switching pulse in the positive direction, a U pulse is a non-switched pulse in the positive direction, an N pulse is a switching pulse in the negative direction, and a D pulse is a non-switched pulse in the negative direction.
An actual oscilloscope waveform is shown in FIG. 2B, in which the P, P.sub.A, U, U.sub.A, N, N.sub.A, D, and D.sub.A charge components are shown for a PZT (lead zirconate titanate) ferroelectric capacitor.
It is important to note that the peak voltage of the pulse sequence 24 shown in FIG. 2A is ideally two to three times the "coercive voltage" associated with the ferroelectric film under test. The "coercive voltage" is shown as points 38 (negative coercive voltage -V.sub.C) and 40 (positive coercive voltage +V.sub.C) along the x-axis or voltage axis of the hysteresis loop 36 plotted in FIG. 3. Points 42 and 44 on hysteresis loop 36 define the two stable states of the ferroelectric film after an externally applied electric field has been removed. Point 42 is generally referred to as an "up" polarization state, and point 44 is generally referred to as a "down" polarization state. These two points 42 and 44 can be arbitrarily defined as a logic one and a logic zero in a one-transistor, one-capacitor ("1T-1C") ferroelectric memory cell, and are compared against a reference level. In a two-transistor, two-capacitor ("2T-2C") ferroelectric memory cell (best seen in FIG. 7), the cell is self-referencing. In this case, the two capacitors are always set in a complementary data state, which means that one capacitor is at point 42 and the other is at point 44. To read the memory, the two capacitors are compared to one another to determine which capacitor is polarized up and which capacitor is polarized down. For example, in reference to the capacitors of FIG. 7, a logic one could be defined as capacitor 126 polarized up and capacitor 128 polarized down, in which case a logic zero would be defined as capacitor 126 polarized down and capacitor 128 polarized up.
The relationship of the individual pulses in the "PUND" characterization waveform and the ferroelectric hysteresis loop is shown in FIGS. 4A-4D and FIGS. 4E-4H. (Note that the "relaxation" property of ferroelectric films, in which a partial dimunition of the polarization magnitudes occurs after the applied external field is removed, is not shown in these figures.) FIGS. 4A-4D are four hysteresis loops showing a partial loop traversal (charge vs. applied voltage) corresponding to the individual pulses identified in the pulse sequences of FIGS. 4E-4H. In the hysteresis loop 50 of FIG. 4A, the ferroelectric capacitor is initially in a down polarization state. Upon the application of a positive-going P pulse 58 shown in FIG. 4E, the loop is traversed as shown, and the polarization state is switched to an up polarization state. The P and P.sub.A charge components are respectively associated with the leading and trailing edges of the P pulse 58 shown in FIG. 4E. In the hysteresis loop 52 of FIG. 4B, the ferroelectric capacitor is in an up polarization state. Upon the application of a positive-going U pulse 60 shown in FIG. 4F, the loop is traversed as shown, but the polarization state remains in the up polarization state. The U and U.sub.A charge components (which are "linear" charge components) are respectively associated with the leading and trailing edges of the U pulse 60 shown in FIG. 4F. In the hysteresis loop 54 of FIG. 4C, the ferroelectric capacitor is in an up polarization state. Upon the application of a negative-going N pulse 62 shown in FIG. 4G, the loop is traversed as shown, and the polarization state is switched to a down polarization state. The N and N.sub.A charge components are respectively associated with the leading and trailing edges of the N pulse 62 shown in FIG. 4G. In the hysteresis loop 56 of FIG. 4D, the ferroelectric capacitor is in a down polarization state. Upon the application of a negative-going D pulse 64 shown in FIG. 4H, the loop is traversed as shown, but the polarization state remains in the down polarization state. The D and D.sub.A charge components are respectively associated with the leading and trailing edges of the D pulse 64 shown in FIG. 4H.
The N and P pulses produce charge components that have linear and non-linear "switched" components, while the D and U pulses produce charge components that have only the linear or "non-switched" components.
A crucial property of nonvolatile semiconductor memories, and ferroelectric memories in particular is retention in the absence of power. Retention is the ability to maintain a given data state between the time the data state is written and when it is subsequently read. A certain data state is written into a ferroelectric capacitor, or, in the case of a two-transistor, two-capacitor ("2T-2C") memory cell, a complementary data state. After a specified period of time, and at temperature, if desired, the data state is read to determine whether or not the original data state has been retained in the memory cell. Retention can be further characterized into an ability to maintain the same state (same state="SS") data or charge (Q.sub.SS) and an ability to read the opposite state data (opposite state="OS") or charge (Q.sub.OS) after maintaining an original data state for an extended period of time. Failure to maintain the same data state rarely occurs, and failures are usually related to operation at elevated temperatures near the Curie point in which the ferroelectric material tends to become paraelectric. A small Q.sub.OS charge indicates the failure of a ferroelectric memory cell to read an opposite data state. This failure mechanism is known as "imprint", and is frequently the source of failure in a ferroelectric memory. Imprint is the inability to maintain an opposite data state once an initial data state has been stored under time and temperature stress, i.e. the original data state is preferred or has been "imprinted" into the ferroelectric capacitor or film.
Prior art techniques for testing retention in a ferroelectric film or capacitor included observing the ferroelectric material after a time and temperature interval for the presence of a hysteresis loop, single pulse testing, exclusively concentrating on the same state aspect of retention, one capacitor tests, and other tests that generally did not emulate the functionality of a ferroelectric capacitor in an actual memory circuit. Further, these tests did not generate graphical predictions for charge loss over time.
What is desired is a testing technique that can fully characterize the time and temperature dependence of retention performance, and in particular the resistance to the imprint failure mechanism, so that the electrical performance of a ferroelectric memory can be predicted.